1. Field of the Invention
The present invention relates to a semiconductor integrated circuit with low power consumption applicable to portable electronic equipment or the like to prolong the lifetime of its battery.
2. Description of Related Art
As the portable equipment has been advancing and developing recently, large-scale integration (LSI) circuits of lower power consumption are required to prolong the lifetime of the battery loaded onto the equipment. One of effective techniques to reduce the consumed power is to drop the operating voltage. Since the consumed power is the product of voltage and current, the operating voltage reduction can decrease both voltage and current. Thus, this is generally thought to give a square effect.
However, MOSFETs constituting the LSI have a characteristic that their operating speed falls as their supply voltage drops. The characteristic is due to the fact that their threshold voltage cannot be imprudently lowered even if the supply voltage is dropped. This is because reducing the threshold voltage will increase the leakage current of the MOSFETs in the nonconducting state, which will increase the consumed power instead of saving power. To solve such a problem, the following conventional methods are taken.
FIG. 7 shows a circuit operating at a low voltage employing so-called MT-CMOS (Multi-threshold CMOS), which is disclosed in Japanese patent application laid-open No. 7-212218/1995. In this figure, the reference numerals 1, 2 and 5 each designate a p-channel MOSFET, and 3, 4 and 6 each designate an n-channel MOSFET. The absolute value of the threshold voltage of the p-channel MOSFETs 1 and 2 are set lower than that of the p-channel MOSFET 5, and the absolute value of the threshold voltage of the n-channel MOSFETs 3 and 4 are set lower than that of the n-channel MOSFET 6 (in the following description, the term "threshold voltage" refers to its absolute value). The MOSFETs 1-4 constitute a combination circuit 11, a two input NAND gate. The p-channel MOSFET 5 is connected across a supply voltage 12 and a virtual power supply line 9 with its gate receiving a control signal CSB1, and the n-channel MOSFET 6 is connected across a ground line 10 and a ground 13 with its gate receiving a control signal CS1.
Next, the operation will be described.
To operate the combination circuit 11 consisting of the two input NAND gate, the control signal CS1 is placed at a high level, and its inverted signal, the control signal CSB1 is placed at a low level. Thus, both the p-channel MOSFET 5 and n-channel MOSFET 6 conduct, so that the virtual power supply line 9 is pulled up to a voltage V.sub.DD of the supply voltage 12, and the ground line 10 is pulled down to the voltage V.sub.GND of the ground voltage 13. As a result, the combination circuit 11 performs the normal NAND operation. In this case, since the threshold voltages (absolute value) of the MOSFETs 1-4 have been set low, high speed operation is achieved even if the voltage V.sub.DD of the supply voltage 12 is low.
On the other hand, when the combination circuit 11 is idling (sleeping), the control signal CS1 is placed at the low level, and its inverted signal, the control signal CSB1 is placed at the high level. This will cause both the p-channel MOSFET 5 and n-channel MOSFET 6 to be placed at a nonconducting state so that the virtual power supply line 9 and ground line 10 are disconnected from the supply voltage 12 and ground 13, respectively. In this case, since the threshold voltages (absolute value) of the p-channel MOSFET 5 and n-channel MOSFET 6 have been set higher than those of the MOSFET 1-4, the leakage current is suppressed at a small value.
Generally speaking, the leakage current across the source and drain increases exponentially against the gate voltage in the region in which the gate-source voltage of a MOSFET is lower than the threshold voltage. Accordingly, the leakage current can be greatly reduced during idling of the combination circuit 11 by setting the threshold voltages of the MOSFETs 5 and 6 at values different from those of the MOSFETs 1-4. Although the foregoing description is provided when the combination circuit 11 is a two input NAND gate, a similar discussion holds true for all LSIs of any types and scales.
Although the conventional low operating voltage semiconductor integrated circuit thus constructed operates normally when it is applied to a combination circuit like the two input NAND circuit, in which its output is determined by a combination of its inputs, it has a problem in that it operates erroneously when applied to a sequential circuit having a function of holding a previous state.
FIG. 8 shows a latch circuit as an example of the sequential circuit, in which two inverters have their inputs and outputs cross-connected. In FIG. 8, the reference numerals 14 and 15 each designate a p-channel MOSFET, and 16 and 17 each designate an n-channel MOSFET, both of which have a low threshold voltage (absolute value). The reference numeral 5 designates a p-channel MOSFET, and 6 designates an n-channel MOSFET, both of which have a high threshold voltage (absolute value). The MOSFETs 14-17 constitute a sequential circuit 20 having a pair of memory nodes 18 and 19, one of which is placed at a high level while the other of which is placed at a low level, thus keeping an input value.
Next, the operation will be described.
When the control signal CS1 is placed at the high level and the CSB1 is placed at the low level, the sequential circuit 20 operates normally and holds the written data correctly. In addition, since the threshold voltages of the p-channel MOSFETs 14 and 15, and the n-channel MOSFETs 16 and 17 are both low, high speed writing to and reading from the nodes 18 and 19 can be achieved.
On the other hand, when the sequential circuit 20 is set idling (sleeping) by placing the control signal CS1 at the low level and the CSB1 at the high level, the leakage current is reduced. This will corrupt the data of the nodes 18 and 19 because the leakage current of the MOSFETs 5 and 6 is lower than the leakage currents of the MOSFETs 14-17 in this case. More specifically, assuming that the node 18 is to be placed at the high level and the node 19 is to be placed at the low level, the p-channel MOSFET 15 and n-channel MOSFET 16 of the four MOSFETs 14-17 must be turned off and the remaining two must conduct. However, the high level of the node 18 falls and the low level of the node 19 rises owing to the leakage current flowing through the p-channel MOSFET 15 and n-channel MOSFET 16. This continues until the levels of the nodes 18 and 19 becomes equal, and hence the data to be held is lost. Thus, the conventional low operating voltage semiconductor integrated circuit has a problem in that the data of the sequential circuit is eliminated.